Buffer insertion is an essential technique for reducing interconnect delay in submicron
circuits. Though it is a well researched area, there is a need for robust and
effective algorithms to perform buffer insertion at the circuit level. This thesis proposes
a new buffer insertion algorithm for large circuits. The algorithm finds a buffering
solution for the entire circuit such that buffer cost is minimized and the timing
requirements of the circuit are satisfied. The algorithm iteratively inserts buffers in
the circuit improving the circuit delay step by step. At the core of this algorithm are
very simple but extremely effective techniques that constructively guide the search
for a good buffering solution. A flexibility to adapt to the user's requirements and the
ability to reduce the number of buffers are the strengths of this algorithm. Experimental
results on ISCAS85 benchmark circuits show that the proposed algorithm, on
average, yields 36% reduction in the number of buffers, and runs three times faster
than one of the best known previously researched algorithms.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/4674 |
| Date | 25 April 2007 |
| Creators | Waghmode, Mandar |
| Contributors | Shi, Weiping |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | 397791 bytes, electronic, application/pdf, born digital |
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