This work deals with design and implementation of a methodology for testing RAM memories connected to an FPGA circuit on Combo cards. In theoretical part of the work RAM faults are sorted by the way they affect the function of the memory and the algorithms to detect them are specified. In practical part, the methodology for testing RAM memories located on Combo cards are proposed, implemented and verified. The NetCOPE framework was used for the implementation. Within the NetCOPE structure, the project was divided into a hardware accelerated application for an FPGA circuit and a software application for a host computer. The project was designed with respect to an easy transfer to other versions of Combo cards.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:221009 |
| Date | January 2014 |
| Creators | Šulc, Tomáš |
| Contributors | Oujezský, Václav, Škorpil, Vladislav |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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