Clock Distribution Network (CDN) is an important component of any synchronous logic circuit. The function of CDN is to deliver the clock signal to the clock
sinks. Clock skew is defined as the difference in the arrival time of the clock signal at
the clock sinks. Higher uncertainty in skew (due to PVT variations) degrades circuit
performance by decreasing the maximum possible delay between any two sequential
elements. Aggressive frequency scaling has also led to high power consumption especially in CDN. This dissertation addresses variation and power issues in the design of
current and potential future CDN. The research detailed in this work presents algorithmic techniques for the following problems: (1) Variation tolerance in useful skew
design, (2) Link insertion for buffered clock nets, (3) Methodology and algorithms for
rotary clocking and (4) Clock mesh optimization for skew-power trade off.
For clock trees this dissertation presents techniques to integrate the different
aspects of clock tree synthesis (skew scheduling, abstract topology and layout embedding) into one framework- tolerance to variations. This research addresses the issues
involved in inserting cross-links in a buffered clock tree and proposes design criteria
to avoid the risk of short-circuit current. Rotary clocking is a promising new clocking
scheme that consists of unterminated rings formed by differential transmission lines.
Rotary clocking achieves reduction in power dissipation clock skew. This dissertation
addresses the issues in adopting current CAD methodology to rotary clocks. Alternative methodology and corresponding algorithmic techniques are detailed. Clock
mesh is a popular form of CDN used in high performance systems. The problem
of simultaneous sizing and placement of mesh buffers in a clock mesh is addressed.
The algorithms presented remove the edges from the clock mesh to trade off skew
tolerance for low power.
For clock trees as well as link insertion, our experiments indicate significant reduction in clock skew due to variations. For clock mesh, experimental results indicate
18.5% reduction in power with 1.3% delay penalty on a average. In summary, this dissertation details methodologies/algorithms that address two critical issues- variation
and power dissipation in current and potential future CDN.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-1250 |
| Date | 15 May 2009 |
| Creators | Venkataraman, Ganesh |
| Contributors | Hu, Jiang |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Dissertation, text |
| Format | electronic, application/pdf, born digital |
Page generated in 0.0021 seconds