Submitted by Setor de Tratamento da Informa??o - BC/PUCRS (tede2@pucrs.br) on 2016-11-29T15:18:25Z
No. of bitstreams: 1
DIS_AUGUSTO_CALCANHOTTO_MENGARDA_COMPLETO.pdf: 1382858 bytes, checksum: 5dd4fe54ce6f97a19b3688711c9ad7c2 (MD5) / Made available in DSpace on 2016-11-29T15:18:25Z (GMT). No. of bitstreams: 1
DIS_AUGUSTO_CALCANHOTTO_MENGARDA_COMPLETO.pdf: 1382858 bytes, checksum: 5dd4fe54ce6f97a19b3688711c9ad7c2 (MD5)
Previous issue date: 2016-08-31 / Conselho Nacional de Pesquisa e Desenvolvimento Cient?fico e Tecnol?gico - CNPq / Digital Video Broadcasting ? Satellite Generation 2 (DVB-S2) standard is widely adopted for militar and civil communication. Due to the long distance between transmitter and receiver, satellite communication links operate with low signal to noise ratio. Forward Error Correction (FEC) techniques are of particular importance for DVBS2 systems, ensuring the desired performance. This dissertation presents the development of a core, in hardware description language, of a LDPC (Low-Density Parity-Check) codec compatible with the DVB-S2 standard. The developed core operates with two sizes of frames and twenty-one encoding rates, as defined in the DVB-S2 standard. The dissertation addresses the main challenges regarding the codec implementation and how they are faced. Three versions of the proposed architecture are implemented and evaluated. Each version uses a different numerical representation for the codec variables. VHDL simulation results are compared with simulations in C programming language, which uses floating point. The results show that the proposed core has equivalent or superior performance to those works reported in the literature when using the architecture with the smallest numerical representation. However, when evaluated the architecture with the highest numerical representation, the obtained FEC performance is significantly better than those presented in the literature, and are close to the results obtained with 64 bits floating point representation. In addition to the performance evaluation, the use of the FPGA (Field-Programmable Gate Array) resources are presented for each one of the three implemented architectures. The analysis of performance versus FPGA resources is addressed. / O padr?o Digital Video Broadcasting ? Satellite Generation 2 (DVB-S2) ? amplamente utilizado em comunica??es via sat?lite, para opera??es nas ?reas de defesa e de comunica??o civil. Devido ? dist?ncia entre transmissor e receptor, enlaces de comunica??o via sat?lite operam com baixa rela??o sinal-ru?do. T?cnicas de Forward Error Correction (FEC) s?o de particular import?ncia no desempenho de sistemas DVB-S2, garantindo a performance desejada. Esta disserta??o de mestrado apresenta o desenvolvimento de um core, em l?gica program?vel, de um codec LDPC (Low-Density Parity-Check) compat?vel com o padr?o DVB-S2. O core opera com os dois tamanhos de frames e as vinte e uma taxas de codifica??o previstas no padr?o. A disserta??o aborda os principais desafios de implementa??o do codec em hardware
e como os mesmos s?o enfrentados. Tr?s vers?es da arquitetura proposta s?o implementadas e avaliadas, utilizando diferentes representa??es num?ricas das vari?veis do sistema, em ponto fixo. Os resultados de simula??o do core VHDL s?o balizados atrav?s de simula??es em linguagem de programa??o C, utilizando ponto flutuante. Os resultados obtidos demonstram que o core proposto apresenta desempenho equivalente ou superior aos relatados em literatura quando utilizada a menor representa??o num?rica implementada. No entanto, quando avaliada a arquitetura de maior representa??o num?rica, os resultados do core proposto nesta disserta??o s?o significantemente superiores aos apresentados em literatura, e pr?ximos aos resultados obtidos nas simula??es em C, utilizando representa??o de 64 bits em ponto flutuante. Al?m das avalia??es de desempenho, s?o apresentados os recursos de hardware utilizados para cada uma das tr?s implementa??es propostas, sendo realizada a an?lise quanto a desempenho versus ocupa??o de recursos FPGA (Field-Programmable Gate Array).
| Identifer | oai:union.ndltd.org:IBICT/oai:tede2.pucrs.br:tede/7061 |
| Date | 31 August 2016 |
| Creators | Mengarda, Augusto Calcanhotto |
| Contributors | Castro, Fernando C?sar Comparsi de |
| Publisher | Pontif?cia Universidade Cat?lica do Rio Grande do Sul, Programa de P?s-Gradua??o em Engenharia El?trica, PUCRS, Brasil, Faculdade de Engenharia |
| Source Sets | IBICT Brazilian ETDs |
| Language | Portuguese |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, info:eu-repo/semantics/masterThesis |
| Format | application/pdf |
| Source | reponame:Biblioteca Digital de Teses e Dissertações da PUC_RS, instname:Pontifícia Universidade Católica do Rio Grande do Sul, instacron:PUC_RS |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 207662918905964549, 600, 600, 600, 600, -655770572761439785, 4518971056484826825, -2555911436985713659 |
Page generated in 0.0019 seconds