The advent of many core architectures has coincided with the energy and power
limited design of modern processors. Projections for main memory clearly show
widening of the processor-memory gap. Cache capacity increased to help reduce
this gap will lead to increased energy and area usage and due to small growth in
die size, impede performance scaling that has accompanied Moore's Law to date.
Among the dominant sources of energy consumption is the on-chip memory hierar-
chy, specically the L2 cache and the Last Level Cache (LLC). This work explores
the use of a novel non-volatile memory technology - Spin Torque Transfer RAM
(STT RAM)" for the design of the L2/LLC caches. While STTRAM is a promising
memory technology, it has some limitations, particularly in terms of write energy and
write latencies. The main objectives of this thesis is to use a novel cell design for a
non-volatile 1T1MTJ cell and demonstrate its use at the L2 and LLC cache levels
with architectural optimizations to maximize energy reduction. The proposed cache
hierarchy dissipates significantly lesser energy (both leakage and dynamic) and uses
less area in comparison to a conventional SRAM based cache designs.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/42715 |
| Date | 23 August 2011 |
| Creators | Rasquinha, Mitchelle |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.002 seconds