Abstract
The tremendous progress in all aspects of signal processing technology has naturally been accompanied by a corresponding development of arithmetic techniques to provide high-speed operations at reasonable complexity. In the past, many architectural design efforts have focused on maximizing performance for frequently executed simple arithmetic operations such as addition and multiplication while left other rarely used operations ignored.
In this dissertation, we firstly propose two design approaches for 64-b carry-lookahead adders (CLA) using a two-phase clocking dynamic CMOS logic since fast adders are the key elements in many digital circuits. Secondly, we place emphasis on the inner product operation since it is one of the most frequently used mathematical operations in the computation of digital neural networks. A ratioed 3-2 compressor is also presented to resolve several physical design problems that are not fully considered or implemented in previous research works. Finally we propose several fast 64b/32b integer dividers because the integer division is unavoidable in many important signal-processing applications.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0516100-103030 |
| Date | 16 May 2000 |
| Creators | Huang, Chenn-Jung |
| Contributors | Sying-Jyan Wang, Wen-Shyen Chen, Jyh-Shing Roger Jang, Wei-Kuang Lai, Chua-Chin Wang, Chung-Ming Huang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0516100-103030 |
| Rights | withheld, Copyright information available at source archive |
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