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Koevoluční algoritmus v FPGA / Coevolutionary Algorithm in FPGA

This thesis deals with the design of a hardware acceleration unit for digital image filter design using coevolutionary algorithms. The first part introduces reconfigurable logic device technology that the acceleration unit is based on. The theoretical part also briefly characterizes evolutionary and coevolutionary algorithms, their principles and applications. Traditional image filter designs are compared with the biologically inspired design methods. The hardware unit presented in this thesis exploits dual MicroBlaze system extended by custom peripherals to accelerate cartesian genetic programming. The coevolutionary image filter design is accelerated up to 58 times. The hardware platform functionality in the task of impulse noise filter design and edge detector design has been empirically analyzed.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:236407
Date January 2013
CreatorsHrbáček, Radek
ContributorsVašíček, Zdeněk, Drahošová, Michaela
PublisherVysoké učení technické v Brně. Fakulta informačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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