Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an
experimental approach. The benchmark circuits are used not only to compare different
architectures, but also to ensure that the FPGA is sufficiently flexible to implement the desired variety of circuits.
The most common benchmark circuits used for architectural research are circuits
from the Microelectronics Center of North Carolina (MCNC). These circuits are small;
they occupy less than 3% [5] of the largest available commercial FPGA. Moreover, these
circuits are more representative of the glue logic circuits that were targets of early devices.
This contrasts with the trend towards implementing Systems on Chip (SoCs) on FPGAs
where several functional modules are integrated into a single circuit which is mapped onto one device.
In this thesis, we develop a synthetic system-level circuit generator that connects pre-existing circuits in a realistic manner to build large netlists that share the characteristics of real SoC circuits. This generator is based on a survey of contemporary circuit designs from industrial and academic sources. We demonstrate that these system-level circuits scale well and that their post-routing characteristics match the results of large pre-existing
benchmarks better than the results of circuits from previous synthetic generators.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:BVAU./2812 |
| Date | 05 1900 |
| Creators | Mark, Cindy |
| Publisher | University of British Columbia |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Format | 910564 bytes, application/pdf |
Page generated in 0.0023 seconds