Security is a primary concern in this era of pervasive computing. Hardware based security mechanisms facilitate the construction of trustworthy secure systems; however, existing hardware security approaches require modifications to the micro-architecture of the processor and such changes are extremely time consuming and expensive to test and implement. Additionally, they incorporate cryptographic security mechanisms that are computationally intensive and account for excessive energy consumption, which significantly degrades the performance of the system. In this dissertation, I explore the domain of hardware based security approaches with an objective to overcome the issues that impede their usability. I have proposed viable solutions to successfully test and implement hardware security mechanisms in real world computing systems. Moreover, with an emphasis on cryptographic memory integrity verification technique and embedded systems as the target application, I have presented energy efficient architectures that considerably reduce the energy consumption of the security mechanisms, thereby improving the performance of the system. The detailed simulation results show that the average energy savings are in the range of 36% to 99% during the memory integrity verification phase, whereas the total power savings of the entire embedded processor are approximately 57%.
| Identifer | oai:union.ndltd.org:unt.edu/info:ark/67531/metadc699986 |
| Date | 08 1900 |
| Creators | Nimgaonkar, Satyajeet |
| Contributors | Gomathisankaran, Mahadevan, Mohanty, Saraju P., Kavi, Krishna M., Fu, Song |
| Publisher | University of North Texas |
| Source Sets | University of North Texas |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
| Format | ix, 108 pages : illustrations (chiefly color), Text |
| Rights | Public, Nimgaonkar, Satyajeet, Copyright, Copyright is held by the author, unless otherwise noted. All rights reserved. |
Page generated in 0.0019 seconds