Pass-transistor logic (PTL) has become an alternative design to traditional CMOS logic design due to its advantages of area/speed/power for some particular circuits such as Exclusive-OR gates. However, the standard cell library used in the logic synthesis of the conventional cell-based design flow does not include PTL circuits. In this thesis, we present a new logic synthesis approaches that consider both the PTL and CMOS cells in order to improve the area and speed performance of the synthesized circuits. In the proposed PTL synthesis, only two types of basic cells are used: a 2-to-1 multiplexer composed of two nMOSs in parallel (MUX) and an inverter with feedback pMOS (P_INV). We propose two methods for mixed PTL/CMOS synthesis. Method 1 finds better choice of library cells from the mixed PTL/CMOS cell library during the technology mapping of the synthesis stage. Method 2 searches for possible CMOS replacement in the pure PTL netlists. Both methods require the efficient inverter reduction method to eliminate unnecessary inverters during the synthesized gate-level netlists. The experimental results show that the mixed PTL/CMOS synthesis can further improve the speed performance compared with pure PTL or pure CMOS synthesis results.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0911106-112323 |
| Date | 11 September 2006 |
| Creators | Lai, Chien-Ming |
| Contributors | Shen-Fu Hsiao, Chung-Ho Chen, Shiann-Rong Kuang, Ko-Chi Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911106-112323 |
| Rights | not_available, Copyright information available at source archive |
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