Majority of the modern day compute intensive applications are heterogeneous
in nature. To support their ever increasing computational requirements, present
day System-on-Chip (SoC) architectures have adapted multicore style of modeling,
thereby incorporating multiple, heterogeneous processing cores on a single chip. The
emerging Network-On-Chip (NoC) interconnect paradigm provides a scalable and
power-efficient solution for communication among multiple cores, serving as a powerful
replacement for traditional bus based architectures. A fast, robust and
exible
emulation platform is the key to successful realization and validation of such architectures
within a very short span of time.
This research focuses on various aspects of Hardware/Software (HW/SW) codesign
for AcENoCs (Accelerated Emulation Platform for NoCs), a Field Programmable
Gate Array (FPGA) accelerated, con gurable, cycle accurate platform for emulation
and validation of NoC architectures. This work also details the design, implementation
and evaluation of AcENoCs' software framework along with the various design
optimizations carried out and tradeoffs considered in AcENoCs' HW/SW codesign
for achieving an optimum balance between emulated network dimensions and emulation
performance. AcENoCs emulation platform is realized on a Xilinx Virtex-5
FPGA. AcENoCs' hardware framework consists of the NoC built using configurable
hardware library components, while the software framework consists of Traffic Generators
(TGs) and their associated source queues, Traffic Receptors (TRs) along with statistics analysis module and dynamically controlled emulation clock generator. The
software framework is implemented using on-chip Xilinx MicroBlaze processor. This
report also describes the interaction between various HW/SW events in an emulation
cycle and assesses AcENoCs' performance speedup and tradeoffs over existing FPGA
emulators and software simulators.
FPGA synthesis results showed that networks with dimensions upto 5x5 could be
accommodated inside the device. Varying synthetic traffic workloads, generated by
TGs, were used to evaluate the network. Real application based traces were also run
on AcENoCs platform to evaluate the performance improvement achieved in comparison
to software simulators. For improving the emulator performance, software
profiling was carried out to identify and optimize the software components consuming
highest number of processor cycles in an emulation cycle. Emulation testcases
were run and latency values recorded for varying traffic patterns in order to evaluate
AcENoCs platform. Experimental results showed emulation speedups in order
of 10000-12000X over HDL (Hardware Description Language) simulators and 14-47X
over software simulators, without sacri cing cycle accuracy.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-12-8657 |
| Date | 2010 December 1900 |
| Creators | Pai, Vinayak |
| Contributors | Gratz, Paul V. |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | application/pdf |
Page generated in 0.0023 seconds