This thesis describes the analysis and comparison of Folded Source-Coupled
Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential
split-level logic gates. The advantages of FSCL are low switching noise and
high operating speed. The effect of voltage and device scaling on these topologies is
evaluated in terms of average delay, power dissipation at maximum frequency,
power-delay-product and current spike noise. Several two-summand adders are
designed and simulated using MOSIS 1-μm CMOS process parameters and evaluations
are performed in terms of area, delay, noise and power dissipation. / Graduation date: 1994
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/36770 |
| Date | 07 February 1994 |
| Creators | Shrivastava, Manu B. |
| Contributors | Kiaei, Sayfe |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.0039 seconds