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Voltage scaling constraints for static CMOS logic and memory cirucits

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1. http://hdl.handle.net/1853/15401
2. 607944

Identifer	oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/15401
Date	05 1900
Creators	Bhavnagarwala, Azeez Jenúddin
Publisher	Georgia Institute of Technology
Source Sets	Georgia Tech Electronic Thesis and Dissertation Archive
Detected Language	English
Type	Dissertation
Rights	Access restricted to authorized Georgia Tech users only.