The primary purpose of this thesis was to design a logical simulation of a communication sub block to be used in the effective communication of digital data between the host and the peripheral devices. The module designed is a Serial interface engine in the Universal Serial Bus that effectively controls the flow of data for communication between the host and the peripheral devices with the emphasis on the study of timing and control signals, considering the practical aspects of them.
In this study an attempt was made to realize data communication in the hardware using the Verilog Hardware Description language, which is supported by most popular logic synthesis tools. Various techniques like Cyclic Redundancy Checks, bit-stuffing and Non Return to Zero are implemented in the design to provide enhanced performance of the module.
| Identifer | oai:union.ndltd.org:fiu.edu/oai:digitalcommons.fiu.edu:etd-2494 |
| Date | 15 January 2003 |
| Creators | Badarinarayana, Terikere |
| Publisher | FIU Digital Commons |
| Source Sets | Florida International University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | FIU Electronic Theses and Dissertations |
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