The Configurable Fault Tolerant Processor (CFTP) team at Naval Postgraduate School (NPS), Monterey, was created to develop, test, and implement reliable computing solutions for the space environment. The CFTP team seeks to design reliable circuits using Field Programmable Gate Arrays (FPGA) to include designs that mitigate the radiation hazards posed to FPGAs. A significant challenge faced by the CFTP team has been the integration and subsequent software development of the CFTP architecture, which includes a "Controller" and an "Experiment" FPGA. This thesis investigates some of the specific design issues that must be considered for future experiments, to include timing between the two FPGAs, and data throughput of the CFTP architecture. Procedures for the development and implementation of experiments are detailed for the benefit of future experimenters who may be new to designing for FGPAs. Lastly, the Controller program is streamlined such that only minor modifications are required by prospective users in order to conform to specific experiments. Over the years the CFTP team has produced several experiments that will provide reliable computing solutions for the space environment. Now, in addition to the "what" is to be used in space, this thesis presents "how" to run them in space.
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/2380 |
| Date | 12 1900 |
| Creators | Caldwell, Gerald W. |
| Contributors | Loomis, Herschel H., Ross, Alan A., Naval Postgraduate School (U.S.)., Electrical and Computer Engineering |
| Publisher | Monterey California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Detected Language | English |
| Type | Thesis |
| Format | xviii, 109 p. : ill. ;, application/pdf |
| Rights | Approved for public release, distribution unlimited |
Page generated in 0.0135 seconds