Processors that employ instruction fusion can improve performance and energy usage beyond traditional processors by collapsing and simultaneously executing dependent instruction chains on the critical path. This paper describes compiler mechanisms that can facilitate and guide instruction fusion in processors built to execute fused instructions. The compiler support discussed in this paper includes compiler annotations to guide fusion, exploring multiple new fusion configurations, and developing scheduling algorithms that effectively select and order fusible instructions. The benefits of providing compiler support for dependent instruction fusion include statically detecting fusible instruction chains without the need for hardware dynamic detection support and improved performance by increasing available parallelism. / A Thesis submitted to the Department of Computer Science in partial fulfillment of the requirements for the degree of Master of Science. / Summer Semester 2017. / July 21, 2017. / compiler, computer architecture, computer science, dependent instruction, parellelism / Includes bibliographical references. / David Whalley, Professor Directing Thesis; Gary Tyson, Committee Member; Xin Yuan, Committee Member.
| Identifer | oai:union.ndltd.org:fsu.edu/oai:fsu.digital.flvc.org:fsu_552035 |
| Contributors | Brunell, Victor J. (authoraut), Whalley, David B. (professor directing thesis), Tyson, Gary Scott (committee member), Yuan, Xin (committee member), Florida State University (degree granting institution), College of Arts and Sciences (degree granting college), Department of Computer Science (degree granting departmentdgg) |
| Publisher | Florida State University |
| Source Sets | Florida State University |
| Language | English, English |
| Detected Language | English |
| Type | Text, text, master thesis |
| Format | 1 online resource (47 pages), computer, application/pdf |
Page generated in 0.0016 seconds