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Functional level modeling of digital devices

Functional level modeling techniques for modeling digital devices that vary in complexity from SSI to LSI are described in this thesis. The vehicle used for modeling is GSP, a general simulation program developed under Dr. J. R. Armstrong at Virginia Tech. These techniques have been used extensively for modeling various devices which include counters, RAMs, ROMs, microprocessor peripheral chips and CPUs. Processors modeled include the Intel 8080, the Zilog Z80 (single chip CPUs) and the Bendix BDX930 (MSI). / Master of Science

Identiferoai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/87252
Date January 1982
CreatorsPuthenpurayil, Venugopal
ContributorsElectrical Engineering
PublisherVirginia Polytechnic Institute and State University
Source SetsVirginia Tech Theses and Dissertation
Languageen_US
Detected LanguageEnglish
TypeThesis, Text
Formatvii, 145, [1] leaves, application/pdf, application/pdf
RightsIn Copyright, http://rightsstatements.org/vocab/InC/1.0/
RelationOCLC# 9274107

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