The purpose of this study is to explore the relationship between hit ratio of cache memory and design parameters. Cache memories are widely used in the design of computer system architectures to match relatively slow memories against fast CPUs. Caches hold the active segments of a program which are currently in use. Since instructions and data in cache memories can be referenced much faster than the time required to access main memory, cache memories permit the execution rate of the machine to be substantially increased. In order to function effectively, cache memories must be carefully designed and implemented. In this study, a trace-driven simulation study of direct mapped, associative mapped and set-associative mapped cache memories is made. In the simulation, cache fetch algorithm, placement policy, cache size and various parameters related to cache design and the resulting effect on system performance is investigated. The cache memories are simulated using the C language and the simulation results are analyzed for the design and implementation of cache memories. / Department of Physics and Astronomy
| Identifer | oai:union.ndltd.org:BSU/oai:cardinalscholar.bsu.edu:handle/183754 |
| Date | January 1989 |
| Creators | Xiong, Bo |
| Contributors | Ball State University. Dept. of Physics and Astronomy., Place, Ralph L. |
| Source Sets | Ball State University |
| Detected Language | English |
| Format | iv, 55, [52] leaves : ill. ; 28 cm. |
| Source | Virtual Press |
Page generated in 0.0092 seconds