Design and evaluation of a technology-scalable architecture for instruction-level parallelism

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1. http://hdl.handle.net/2152/3534
2. 191736114

Tags

Computer architecture--Design

Computer architecture--Evaluation

High performance processors--Evaluation

Threads (Computer programs)

Additional Fields

Identifer	oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/3534
Date	28 August 2008
Creators	Nagarajan, Ramadass, 1977-
Contributors	Burger, Douglas C., Ph. D.
Source Sets	University of Texas
Language	English
Detected Language	English
Type	Thesis
Format	electronic
Rights	Copyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.