Several papers propose the use of on-line arithmetic for signal processing applications
implemented on FPGAs. Although those papers provide reasonable arguments for
the use of on-line arithmetic, they give only inadequate or incomplete comparisons of
the proposed on-line designs to other state of the art solutions on FPGAs.
In this thesis, the design, implementation and evaluation of on-line modules and
networks for DSP applications, using FPGAS as the target technology, are shown. The
presented designs of the modules are highly optimized for the target hardware, which allows
a significant increase in efficiency compared to standard on-line designs. The design
process for the networks of on-line modules is described in detail, and a methodology to
analyze the dataflow and timing is presented.
A comparison of on-line signal processing solutions with other approaches. that are
available as IP building blocks or components, is given. It is shown that on-line designs
are better in terms of latency but that they can not compete in terms of throughput and
area for basic applications like FIR filters. However, it is also shown that on-line designs
are able to overtake other approaches as the applications become more sophisticated.
e.g. when data dependencies exist, or when non constant multiplicands restrict the use
of other approaches, such as serial distributed arithmetic. For these applications, online
arithmetic shows, compared to other designs, a lower latency and a significant area
reduction, while maintaining a high throughput.
Several properties of algorithms for which on-line arithmetic is advantageous are
identified in this thesis. With this information, it is possible to determine if an on-line
solution for an application should be considered.
The conclusions are based on experimental data collected using CAD tools for
the Xilinx XC4000 family of chips. All the designs are synthesized for the same type
of devices for comparison, avoiding rough estimates of the system performance. This
generates a more reliable comparison allowing designers to decide between on-line or
conventional approaches for their DSP designs. / Graduation date: 2002
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/30996 |
| Date | 07 June 2001 |
| Creators | Galli, Reto |
| Contributors | Tenca, Alexandre F. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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