Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm.
A mixed-signal IC implementation has been chosen for the parallel MDFE. The
differential current signals from the feedback equalizer are subtracted from the forward
equalizer output at the summing node to cancel the non-causal ISI. A high-speed
comparator with 6 bit resolution is used after the cancellation to detect the signal which
contains no ISI.
In this thesis, a description of the parallel MDFE structure and decision feedback
equalization algorithm are presented. The design of a high-speed summing circuitry and
a high-speed comparator are discussed. The same comparator design is used for the flash
analog-to-digital converter (ADC) which generates error signals for adaptation.The
circuits design and layout were carried out in an HP 1.2-��m n-well CMOS process. / Graduation date: 1998
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/34282 |
| Date | 23 June 1997 |
| Creators | Gao, Hairong |
| Contributors | Allstot, David J. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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