Field Programmable Gate Arrays (FPGAs) provide a reconfigurable asset in the design of space computing. â Hardwareâ configurations are stored in FPGA memory elements, which are susceptible to Single Event Upsets (SEUs). What is the best way to detect and mitigate SEUs and correct them before they become functional errors? The Configurable Fault Tolerant Processor (CFTP) consists of a controller FPGA (X1) controlling an experiment FPGA (X2), which can be used to test different fault-mitigation techniques. This focus of this thesis was to develop and execute a radiation test plan to evaluate different experiments in a proton radiation beam at Crocker Nuclear Laboratory, Davis, CA. A shift register was designed to determine a proton flux conducive to SEU observation. The shift register was also modified to create two additional configurations, implemented with the memory elements of the Look-Up Table and Flip-flops within an FPGA Configurable Logic Block. The data collected from this program was then analyzed for SEU rates and fault susceptibility. This data was extrapolated using a radiation environment model to predict the on-orbit SEU-rate for CFTP in the NPSAT1 orbit of 560 km, 35.4 degrees inclination, as well as Virtex II FPGAs and at 1000 and 1500 km altitudes.
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/1829 |
| Date | 12 1900 |
| Creators | Coudeyras, James C. |
| Contributors | Loomis, Herschel H., Ross, Alan A., Naval Postgraduate School (U.S.)., Department of Electrical and Computer Engineering |
| Publisher | Monterey, California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Detected Language | English |
| Type | Thesis |
| Format | xxii, 141 p. : col. ill. ;, application/pdf |
| Rights | Approved for public release, distribution unlimited |
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