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Optimization of a cyclostationary signal processing algorithm using multiple field programmable gate arrays on the SRC-6 reconfigurable computer

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 2009. / Thesis Advisor(s): Fouts, Douglas J. ; Pace, Phillip E. "September 2009." Description based on title screen as viewed on November 6, 2009. Author(s) subject terms: SRC-6, reconfigurable computers, FPGA, cyclostationary processing, Time- Smoothing FFT Accumulation Method. Includes bibliographical references (p. 101-102). Also available in print.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/463653667
Date January 2009
CreatorsSimon, Wesley A.
PublisherMonterey, California : Naval Postgraduate School,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
Source(3 MB)

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