The growth of applications for embedded processors has spawned a need for
highly configurable devices. Custom microprocessors have long life cycles for a
fast paced market, where as off-the-shelf designs often do not provide the level of
configuration, nor the ability to allow system-on-chip designs. This paper presents
a description for a software environment that allows designers to provide
configuration options for a design, and responds by dynamically reconfiguring the
environment to provide a ready to test design. A background survey is provided on
current embedded RISC architectures, along with a proposed new embedded ISA
and a cycle-level simulator. Justification is presented for a new instruction format
to reduce code size with little loss to performance. A manual is also provided for
the new ISA. / Graduation date: 2003
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/32051 |
| Date | 02 May 2003 |
| Creators | Matson, John Mark |
| Contributors | Lee, Ben |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.0064 seconds