The parasitic components of MOS switches at high speeds affect the linearity
and resolution of CMOS sample and hold circuits. CCD-based circuit design can
offer good performance at high speeds. This thesis presents the design of sample
and hold circuits using charge-coupled device structures in a standard CMOS process.
Three sample and hold circuits have been built and tested for linearity and
speed performance. The CCD S/Hs have been characterized using a continuous-time
integrator and a Δ∑ ADC. The CCDs, with a switched capacitor amplifier
at the output, achieve an SFDR of 54dB for an input signal V[subscript in]=2.6V+0.4Vpp at
f[subscript in]=10.1KHz. / Graduation date: 2003
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/29928 |
| Date | 07 August 2002 |
| Creators | Ghatak, Kalyan Brata |
| Contributors | Fiez, Terri S. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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