Switching device power losses place critical limits on the design and performance of high-frequency integrated DC-DC converters. Especially, the layout of metal interconnects in lateral power MOSFETs has a profound effect on their on-resistances and conduction power losses. This thesis presents an analytical interconnect modeling and layout optimization technique for large-area power MOSFETs. The layout optimization of 24V LDMOS transistors in the area of 1 mm2 has achieved an improvement of 55 % in its on-resistance. The simulation result has been verified by experimental measurements on a test chip fabricated in TSMC 0.25 µm HV CMOS technology. In addition, this thesis presents an optimized output stage design methodology for the implementation of a 4 MHz, 12V to 1V integrated DC-DC converter. A segmented output stage scheme is employed to increase the converter efficiency at light load conditions. The peak efficiency of 84% was achieved at load current of 2 A.
| Identifer | oai:union.ndltd.org:TORONTO/oai:tspace.library.utoronto.ca:1807/65440 |
| Date | 18 June 2014 |
| Creators | Lee, Junmin |
| Contributors | Ng, Wai Tung |
| Source Sets | University of Toronto |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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