Integration of VHDL simulation and test verification into a Process Model Graph design environment /

Description

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 116-117). Also available via the Internet.

Links & Downloads

1. http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/

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Additional Fields

Identifer	oai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/31059192
Date	January 1994
Creators	Dailey, David M.,
Source Sets	OCLC
Language	English
Detected Language	English
Source	This resource online