In this research, an AHPL (A Hardware Programming Language) based automation system is used to design and verify the Intel-8080 microprocessor from the RTL (Register Transfer Level) hardware description through the network list of transistors. The HPSIM is used as a RTL simulator which interprets the AHPL description and executes the connections, branches, and register transfer, and prints line or register values for each circuit clock period. After the AHPL description has been translated to switch-level link list, ESIM is applied for more detailed simulation to ensure the digital behavior in this microprocessor design is correct. The ESIM is an event-driven switch-level simulator which accepts commands from the user, and executes each command before reading the next one. After performing these different levels of simulations, a comparison is discussed at the end.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/276532 |
| Date | January 1987 |
| Creators | Lai, Jiunn-Yiing, 1958- |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Thesis-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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