Multipliers are used in most arithmetic computing
systems such as 3D graphics, signal processing, and etc. It
is inherently a slow operation as a large number of partial
products are added to produce the result. There has been
much work done on designing multipliers [1]-[6]. In first
stage, Multiplication is implemented by accumulation of
partial products, each of which is conceptually produced
via multiplying the whole multi-digit multiplicand by a
weighted digit of multiplier. To compute partial products,
most of the approaches employ the Modified Booth
Encoding (MBE) approach [3]-[5], [7], for the first step
because of its ability to cut the number of partial products
rows in half. In next step the partial products are reduced
to a row of sums and a row of caries which is called
reduction stage. / Multiplication is one of the major bottlenecks in most digital
computing and signal processing systems, which depends on the
word size to be executed. This paper presents three deferent
designs for three-operand 4-bit multiplier for positive integer
multiplication, and compares them in regard to timing, dynamic
power, and area with classical method of multiplication
performed on today architects. The three-operand 4-bit
multipliers structure introduced, serves as a building block for
three-operand multipliers in general
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/219513 |
| Date | 01 April 2012 |
| Creators | Nezhad, Mohammad Reza Reshadi, Navi, Kaivan |
| Contributors | Department of Electrical and Computer engineering, Shahid Beheshti University, G.C., Tehran, Tehran 1983963113, Iran, Faculty of Department of Computer engineering, University of Isfahan, Isfahan, Isfahan 8174673440, Iran |
| Publisher | IJCSN |
| Source Sets | University of Arizona |
| Language | English |
| Detected Language | English |
| Type | Article, Technical Report |
| Relation | IJCSN-2012-1-2-9, http://ijcsn.org/publications.html |
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