A new 32-bit reconfigurable FPGA implementation of AES algorithm is presented in this
thesis. It employs a single round architecture to minimize the hardware cost. The combinational
logic implementation of S-Box ensures the suitability for non-Block RAMs
(BRAMs) FPGA devices. Fully composite field GF((24)2) based encryption and keyschedule
lead to the lower hardware complexity and convenience for the efficient subpipelining.
For the first time, a subpipelined on-the-fly keyschedule over composite field GF((24)2)
is applied for the all standard key sizes (128-, 192-, 256-bit). The proposed architecture
achieves a throughput of 805.82Mbits/s using 523 slices with a ratio throughput/slice of
1.54Mbps/Slice on Xilinx Virtex2 XC2V2000 ff896 device. / ix, 77 leaves : ill. ; 29 cm.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:ALU.w.uleth.ca/dspace#10133/778 |
| Date | January 2008 |
| Creators | Li, Ke, University of Lethbridge. Faculty of Arts and Science |
| Contributors | Li, Hua |
| Publisher | Lethbridge, Alta. : University of Lethbridge, Deptartment of Mathematics and Computer Science, 2008, Arts and Science, Mathematics and Computer Science |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | Thesis (University of Lethbridge. Faculty of Arts and Science) |
Page generated in 0.0026 seconds