This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:219090 |
| Date | January 2011 |
| Creators | Štraus, Pavel |
| Contributors | Kováč, Michal, Kubíček, Michal |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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