A dual-mode second-order Multirate Multibit Sigma Delta (MM-SD) modulator is implemented in a 90nm
digital CMOS process for application in the baseband path of RF receivers. Low power consumption is achieved through a new integrator structure and a dedicated timing scheme along with aggressive capacitor scaling in the second stage of the modulator loop. Fabricated prototype achieves 68.6dB peak Signal-to-Noise and Distortion ratio (SNDR) in the 200 kHz GSM band and requires 1.1mA of total current from a
1.5V supply. This dual-mode design also achieves 42.8dB SNDR in the 1.94 MHz WCDMA band with only
1.9mA of total current consumption.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/7104 |
| Date | 18 April 2005 |
| Creators | Altun, Oguz |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
| Format | 1067977 bytes, application/pdf |
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