Chan Wing-kin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-72). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.ii / 摘要 --- p.iv / Acknowledgements --- p.v / Table of Contents --- p.vi / List of Figures --- p.viii / List of Tables --- p.x / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Communication Systems --- p.1 / Chapter 1.2 --- Soft-output Viterbi Decoder and Turbo Code --- p.2 / Chapter 1.3 --- Iterative Decoding --- p.3 / Chapter 1.4 --- Motivation --- p.3 / Chapter 1.5 --- Organization of the Thesis --- p.4 / Chapter Chapter 2 --- Self-timed Circuit Design Methodology --- p.5 / Chapter 2.1 --- Properties of Self-Timed Design --- p.5 / Chapter 2.2 --- Bundled-data Protocol --- p.7 / Chapter 2.3 --- Two-phase verses Four-phase Handshaking --- p.8 / Chapter 2.4 --- Completion-Detection and Delay Match --- p.9 / Chapter 2.5 --- Muller Pipeline --- p.11 / Chapter 2.6 --- Design of the Adder --- p.12 / Chapter 2.6.1 --- Basic Structure --- p.12 / Chapter 2.6.2 --- Carry Chain and Completion Detection --- p.12 / Chapter Chapter 3 --- SOVA Theory --- p.15 / Chapter 3.1 --- Convolutional Encoder --- p.15 / Chapter 3.2 --- Hard verse Soft Decision Decoding --- p.17 / Chapter 3.3 --- Soft Output Viterbi Algorithm --- p.17 / Chapter 3.3.1 --- Viterbi Algorithm --- p.17 / Chapter 3.3.2 --- Soft Output Algorithm --- p.20 / Chapter Chapter 4 --- Proposed SOVA Decoder Design --- p.24 / Chapter 4.1 --- Overview --- p.24 / Chapter 4.2 --- SOVA Decoder Architecture --- p.24 / Chapter 4.3 --- Branch Metric Unit --- p.26 / Chapter 4.3.1 --- Branch Metric Generation --- p.26 / Chapter 4.3.2 --- Implementation --- p.27 / Chapter 4.4 --- Add-Compare-Select Unit --- p.28 / Chapter 4.4.1 --- Basics --- p.28 / Chapter 4.4.2 --- Self-timed design --- p.28 / Chapter 4.4.3 --- Metric Normalization --- p.30 / Chapter 4.4.4 --- ACS Unit Implementation --- p.31 / Chapter 4.5 --- Traceback Unit --- p.33 / Chapter 4.5.1 --- Viterbi Algorithm Traceback --- p.33 / Chapter 4.5.2 --- Two Step SOVA --- p.34 / Chapter 4.5.3 --- Past Designs --- p.36 / Chapter 4.5.4 --- New Traceback Architecture --- p.38 / Chapter 4.5.5 --- Traceback operation --- p.40 / Chapter 4.5.6 --- Traceback Implementation --- p.42 / Chapter 4.5.7 --- Control Signals --- p.48 / Chapter Chapter 5 --- Experimental Result and Discussion --- p.54 / Chapter 5.1 --- Chip Fabrication --- p.54 / Chapter 5.2 --- Measurements --- p.61 / Chapter Chapter 6 --- Conclusion --- p.67 / References --- p.69 / Appendix --- p.73 / Pin Assignment of the SOVA test chip --- p.73
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_324950 |
| Date | January 2004 |
| Contributors | Chan, Wing-kin., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, x, 103 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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