隨著工藝尺寸的縮小，集成電路的時序行為變得越來越難以預測，某原因在於各種偏差效應，比如製造偏差、供電電壓波動以及溫度變化。對於傳統的“確保正確“的設計方式，我們需要留出很大的餘量，這就減少了工藝進步帶來的好處。時序監測C Timing Speculation) 因為具有錯誤檢測和更正機制而成為一種很有前景的解決辦法。採用這種方式，電路可以工作在有不太頻繁時序錯誤的情況下。而對於這種時序監視的設計方式，現有的優化方法大多主要是在電路結構確定之後的一些小的改動。因為這些方法無法對電路結構進行改變，所以它們的效果很有限。因此，我們在這篇論文里提出了在電路綜合(synthesis)過程中的一些優化方法，這些方法是能夠改變電路結構的。我們提出的優化方法主要集中在優化電路的硬件開銷和電路性能的方面。我們提出的方法主要包括兩個設計階段。 / 第一個階段是在邏輯綜合(Logic synthesis) 的時候.在邏輯綜合的時候，我們有很大的自由度去根據時序監測的特性來改變電路的結構。如果結合了特殊的實現方法，電路出現時序錯誤的頻率就會得到降低，從而提高了電路的性能。 / 第二個階段是在邏輯綜合之後的后綜合(Post-synthesis) 階段。為了減少時序監測的硬件上的開銷，我們提出了基於retiming 手法的再綜合(resynthesis) 方法.這種方法可以減少可疑寄存器(suspicious FF) 的數量從而降低硬件開銷。另外這種辦法也可以提高電路的吞吐量(throughput) 。為了進一步對電路進行優化，我們挨著又提出了基於rewiring 手法的電路吞吐量優化方法。此外，利用這種方法我們還可以消除部份電路里的短通路(short path) 從而進一步減少電路的硬件開銷。在這個階段，我們仍然具有改變電路結構的靈活性，因此我們的方法具有很好的效果。 / With technology scaling, the timing behavior of integrated circuits (ICs) becomes more unpredictable due to various variation effects, such as manufacturing variability, voltage fluctuations and temperature changes. A large design guard band is therefore reserved to ensure “always correct“ operation for traditional designs, disminishing the benefits of technology scaling. Timing speculation with error detection and correction mechanisms is a promising solution to tackle the above problem. With this technique, circuit can work under infrequent timing errors. The existing optimization techniques for timing speculated circuits are mainly based on some small modifications after the circuit structure is determined. Without the ability to change circuit structure, the efficiency is limited. Therefore, in this thesis we propose optimization techniques during the process of synthesis so that the flexibility is provided to make circuit structural change. Our optimization fo¬cuses on hardware cost and circuit performance and the proposed techniques are included in two design steps. / First step is logic synthesis. During the process of logic synthesis, there is large flexibility to change the circuit structure by considering the features of timing speculation. With intentional strategy the timing error probability can be reduced so as to improve the circuit throughput. / Second step is post-synthesis techniques after logic synthesis. To reduce the hardware cost for timing speculation, we propose a re-synthesis method based on the idea of retiming to reduce the number of suspicious FFs where timing errors mainly happen. This technique can also help to improve the circuit throughput if carefully implemented. To further improve the throughput, we also propose to use rewiring technique which is also called redundancy addition and removal (RAR) to optimize circuit for throughput. Furthermore, this technique can also be used to break down short paths so as to save the hardware cost. During this step, flexibility is also provided to make circuit structural change so that the efficiency is guaranteed. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Liu, Yuxi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 70-76). / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Timing Speculation --- p.1 / Chapter 1.1.1 --- Circuit Timing Problem --- p.1 / Chapter 1.1.2 --- Possible Solution --- p.3 / Chapter 1.1.3 --- Timing Speculation is Promising --- p.4 / Chapter 1.1.4 --- Razor Flip-flop --- p.5 / Chapter 1.2 --- Problems for Timing Speculation --- p.6 / Chapter 1.2.1 --- Hardware Cost of Timing Speculation --- p.7 / Chapter 1.2.2 --- Performance of Timing Speculation --- p.8 / Chapter 1.3 --- Thesis Motivation and Organization --- p.9 / Chapter 1.4 --- Thesis Contributions --- p.11 / Chapter 2 --- Logic Synthesis for Timing Speculation --- p.13 / Chapter 2.1 --- Introduction --- p.13 / Chapter 2.2 --- Preliminaries --- p.14 / Chapter 2.2.1 --- Timing Speculation --- p.14 / Chapter 2.2.2 --- AIG-Based Logic Synthesis --- p.15 / Chapter 2.3 --- Logic Synthesis for Timing Speculation --- p.16 / Chapter 2.3.1 --- Proposed Optimization Metric --- p.17 / Chapter 2.3.2 --- Proposed Logic Synthesis Solution --- p.19 / Chapter 2.4 --- Experimental Results --- p.24 / Chapter 2.4.1 --- Experimental Setup --- p.24 / Chapter 2.4.2 --- Results and Discussion --- p.25 / Chapter 2.5 --- Conclusion --- p.30 / Chapter 3 --- Post-Synthesis Optimization for Timing Speculation --- p.31 / Chapter 3.1 --- Optimization for Timing Speculation by Retiming --- p.32 / Chapter 3.1.1 --- Introduction --- p.32 / Chapter 3.1.2 --- Preliminaries and Motivation --- p.33 / Chapter 3.1.3 --- Reducing Suspicious FFs by Retiming --- p.35 / Chapter 3.1.4 --- Reducing Timing Error Probability by Retiming --- p.41 / Chapter 3.1.5 --- Padding Short Paths --- p.43 / Chapter 3.2 --- Optimization for Timing Speculation by Rewiring --- p.47 / Chapter 3.2.1 --- Introduction --- p.47 / Chapter 3.2.2 --- Preliminaries --- p.48 / Chapter 3.2.3 --- Timing Optimization by Rewiring --- p.52 / Chapter 3.2.4 --- Reduce Hardware Cost by Rewiring --- p.60 / Chapter 3.3 --- Experimental Results --- p.62 / Chapter 3.4 --- Conclusion --- p.66 / Chapter 4 --- Conclusion --- p.68 / Bibliography --- p.76
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_328747 |
| Date | January 2012 |
| Contributors | Liu, Yuxi., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | electronic resource, electronic resource, remote, 1 online resource (ix, 76 leaves) : ill. (some col.) |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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