Ph.D. / Electrical Engineering / The expected unreliability of nano-scale electronic components has renewed interest in the decades-old field of fault-tolerant logic design. Fault-tolerant design makes it possible to build reliable systems from unreliable components. This has spurred recent research into the application of classical FT techniques to nanoelectronics. Meanwhile, the growing gap between logic gate and wire delays, and the growing power consumption of clock generation and distribution circuits, in nanometer-scale silicon integrated circuits has renewed research in asynchronous, or clockless, logic design. This dissertation examines the application of triple modular redundancy (TMR), one of several FT circuit design techniques, to improve the reliability of a variety of clockless circuits and systems. A new fault model, appropriate for clockless circuits is derived and applied to measure the reliability of nonredundant and triplex micropipelines. A new circuit element that combines the functionality of a Muller C-element and a majority gate is introduced to solve special problems at the simplex-triplex interface. The effectiveness of asynchronous FT circuit design strategies based on the results of Monte Carlo simulation experiments with representative circuits modeled in Verilog hardware description language (HDL) is presented.
| Identifer | oai:union.ndltd.org:OREGON/oai:content.ohsu.edu:etd/664 |
| Date | 10 1900 |
| Creators | Lynch, John Daniel |
| Publisher | Oregon Health & Science University |
| Source Sets | Oregon Health and Science Univ. Library |
| Language | English |
| Detected Language | English |
| Type | Text |
| Format | Needs Adobe Acrobat reader to view, PDF, 1372.442 KB |
| Rights | http://www.ohsu.edu/library/etd_rights.shtml |
Page generated in 0.0014 seconds