The era of VLSI design necessitates the development of advanced Computer Aided Design tools. The main objective of this research was to introduce an intelligent automatic Sequential Circuit Test System, SCIRTSS, driven by A Hardware Programming Language, AHPL. SCIRTSS can handle the test vector generation process for VLSI circuits in an early state of the design loop, even before the generation of the final technology dependent network logic list. The driving force of the test generation process is the intelligent search program. The search program, supported by a set of heuristics and an accurate function level simulator, generates the test sequence to propagate the single fault effect to a primary output of the circuit. The test sequence generated is a concatenation of the sequences generated by the repeated searches on the state-space of the design. These sequences are verified by a parallel fault simulator. Design for testability techniques could be used to improve the test sequence generated. This system is user friendly and protable. Several circuits were tested under SCIRTSS, the results of some of them were introduced in this paper.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/187889 |
| Date | January 1984 |
| Creators | MOHSSENIBEHBAHANI, ALAA. |
| Contributors | Hill, Frederick |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | English |
| Detected Language | English |
| Type | text, Dissertation-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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