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Voltage scaling constraints for static CMOS logic and memory cirucits

No description available.
Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/15401
Date05 1900
CreatorsBhavnagarwala, Azeez Jenúddin
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Detected LanguageEnglish
TypeDissertation
RightsAccess restricted to authorized Georgia Tech users only.

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