This thesis includes two topics. The first one is a low-power double-edge triggered flip-flop.The other is a orthogonal frequency division multiplex (OFDM) demodulator compliant with the Digital Video Broadcasting Handheld (DVB-H).
Low-power double-edge triggered flip-flop (DETFF) is based on multi-Vth transistors technique. Since low threshold voltage transistors are able to generate large leakage current, they are suitable to drive big loads. By contrast, high threshold voltage transistors are more appropriate to latch data due to their low leakage. Therefore, a single latch double-edge triggered flip-flop utilizing multi-Vth transistors can be a low power and high speed design without paying the price of large area.
The proposed OFDM demodulator is compliant with the DVB-H standard. The received DVB-H signal is processed by an RF front-end and the following analog-to-digital converter. Then, the digital signal is fed into the demodulator to adjust and calibrate the frequency, timing offset and channel estimation. The proposed DVB-H demodulator is mainly composed of five blocks : symbol timing synchronization block, carrier frequency offset compensation block, fast Fourier transform block, scatter pilot detection block and channel compensation block.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0711107-182754 |
| Date | 11 July 2007 |
| Creators | Shen, Ying-Yu |
| Contributors | Ju-Ya Chen, Chih-Peng Li, Chua-Chin Wang, Sying-Jyan Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0711107-182754 |
| Rights | not_available, Copyright information available at source archive |
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