This thesis is composed of three parts. In the first part, analysis and discussion of phase noise in phase-locked loop is made. Because OFDM upconverter requires high phase noise performance, we therefore study the mechanism of noise suppression in a proposed dual phase-locked loop, and then derive the formula to predict the circuit characteristics. In the second part, experiment and simulation of a dual phase-locked loop is performed for comparison. The experiment uses hybrid circuit combined with related equipment and components to measure the noise suppression characteristics in a dual phase-locked loop. The simulation relies on the component behavioral model in ADS. Comparison between simulation and measurement shows good agreement. In the third part, this thesis carries out a 1.55¡V2.3 GHz frequency synthesizer RFIC design for DVB up-down architecture using TSMC 0.18£gm CMOS process. The test results validate the chip design.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0723109-235001 |
| Date | 23 July 2009 |
| Creators | Tsai, Wen-shiou |
| Contributors | Chie-In Lee, Kang-Chun Peng, Huey-Ru Chuang, Tzyy-Sheng Horng, Sheng-Fu Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723109-235001 |
| Rights | not_available, Copyright information available at source archive |
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