Signal delay estimates for high-speed interconnection nets are formulated using analytical methods. The equations are suitable for estimating delay in interconnects of printed wiring boards and multi-chip modules where the resistance of wires is small. Effects of drivers, receivers, chip interfaces and wires on delay are considered by using simple models. The wires are treated as lossless transmission lines with capacitive discontinuities modeling receiver chip interfaces. Drivers are voltage sources with series resistance. Signal delay consists of line propagation delay and delay due to the change in rise time and reflections at the discontinuities. Various commonly used net topologies are identified and wiring rules and delay predictors provided for each of them. It is shown that interconnect delay can be formulated as a non-linear function of the product of the line characteristic impedance and load capacitance. SPICE simulations are sued to validate analytical derivations.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/278171 |
| Date | January 1992 |
| Creators | Menezes, Karol Fidelis, 1966- |
| Contributors | Palusinski, O. A. |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Thesis-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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