A modularized three-dimensional power electronics environment will become increasingly necessary as power converters are more intertwined with the dynamic desires of modern society. This is driven by ever-changing requirements, combined with the desire for quick design cycles, and then further compounded by the increased penetration of electrified technologies. The high demand for various power converters presents a design, manufacturing, and validation burden which can be lessened with a three-dimensional power electronics environment, where power converters of any arbitrary set of voltage, current, or quantity of independent input/outpt requirements can be assembled from a grouping of pre-existing converter modules. This, however, has drawbacks when compared with bespoke power converter designs. Modularization can be complex, lossy, and large, and the resulting converter's overall efficiency and power density will then suffer. To compensate for these costs of modularization, the individual modules must be first be power dense and efficient, and then the framework for grouping modules together must be simple.
This dissertation first proposes a high performance Power Conversion Unit (PCU) which is achieved through a unique combination of techniques. The first of these techniques is modification to the ubiqutioius buck converter topology in a form of an adjustment to its output filter. This topological modification results in decreased current ripple handling requirements of the filter, which can be used to reduce its volume. The second topological technique is an additional capacitance placed across the drain-source terminals of each FET, which is used to reduce their turn-off switching energy at the expense of their turn-on switching energy. A variable frequency soft-switching scheme is utitlized to prevent the converter from incurring turn-on losses, and a duty cycle compensation scheme is developed to mitigate the distortions caused by this increased drain-source capacitance. Finally, a process for balancing the PCU design parameters that results in a Pareto frontier of efficiency-power density optimal points is defined, one selected, and a protoype PCU constructed and tested in a three-phase inverter configuration.
A framework for the vertical stacking of PCUs is then shown. This framework, named the Manhattan Topology, is a multilevel power converter topology which is defined by a set of series stacked capacitances where there exists a method to transfer power between capacitances. This framework has linear complexity and switching device stress scaling with the number of levels, which yields a simple methodology for grouping modules together in the vertical dimension. Furthermore, it exhibits Partial Power Processing (PPP) characteristics as the power processed internally to the overall converter is less than its output power. This framework is validated for both DC/DC and AC/DC applications and control and conversion of voltages greater than the rating of any individual component within the converter is experimentally demonstrated. Lastly, another three-phase inverter is built using this topological framework and the performance of this vertically-modularized inverter is compared with the non-modularized inverter. It is shown that the three-dimensional modular power electronics environment with optimized PCUs, despite the costs of modularization, is still performance-competitive with the non-modular power electronics environment.
| Identifer | oai:union.ndltd.org:columbia.edu/oai:academiccommons.columbia.edu:10.7916/pe03-yw20 |
| Date | January 2024 |
| Creators | Jahnes, Matthew |
| Source Sets | Columbia University |
| Language | English |
| Detected Language | English |
| Type | Theses |
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