A variable gain, high linearity, low power baseband filter for WLAN applications
is implemented in a 1.5 V 3 V 0.15 ��m CMOS process. This fourth-order
low-pass filter, which is introduced in the transmit channel as a reconstruction filter
between the D/A converter and the mixer, has a measured cut-off frequency of
9 MHz. The active-RC configuration has single amplifier biquads (SABs) to save
power and is implemented using three-stage opamps with nested-Miller compensation
for better linearity. It also features a special ��-to-Tee transformation network
for the resistor arrays, used for frequency or gain trimming, in order to obtain higher
linearity than conventional Sallen-Key circuits. The measured THD for a 2 V [subscript p-p]
signal at 1 MHz is -72 dB. / Graduation date: 2004
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/32350 |
| Date | 15 April 2003 |
| Creators | Ranganathan, Sachin |
| Contributors | Fiez, Terri S. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.002 seconds