The Internet of Things (IoT) is now permeating our daily lives, providing critical data for every decision. IoT architecture consists of multiple layers with unique functions and independent components. Each layer of IoT architecture requires different power sources and power delivery schemes. Therefore, different types of power management architectures are required for individual IoT components. Fortunately, advances in metal oxide semiconductor (MOS) technology have made it possible to implement a variety of high-performance power management architectures.
These power management architectures should not only create the power rails required for IoT components but also serve additional functions depending on the application. The power management architecture of IoT devices needs to support sub-mW- or mW-scale power consumption. In addition, the power management architecture should be either fully integrated on a chip or miniaturized with few passive components to minimize the size of IoT devices. Building-scale data centers, on the other hand, need various power conversion stages. In this scenario, power conversion from an intermediate DC bus to many point of loads (PoL) requires a high conversion ratio DC-DC converter. Because each PoL draws enormous amounts of power, the power management architecture should withstand high currents and include protection circuitry to prevent damage.
This thesis presents research on the design of power management architectures required by IoT devices and data centers. Chapter 2 presents the design and circuit techniques of power management architectures for IoT devices. Chapter 2 outlines a new methodology for co-designing an integrated switched-capacitor (SC) DC-DC converter and a load circuit in ultra-low-power IoT devices. This methodology enables the implementation of an area-efficient fully integrated IoT system-on-chip (SoC) while maintaining high power conversion efficiency (PCE). Chapter 3 presents a 10-output ultra-low-power single-inductor-multiple-output (SIMO) DC-DC buck converter with integrated output capacitors for sub-mW IoT SoCs. Featuring a continuous comparator-based output switch controller and a digital pulse-width modulation (PWM) controller for ultra-low feedback latency, this SIMO converter produces ten independent output voltages with high PCE.
Lastly, in Chapter 4, an integrated programmable gate timing control and gate driver chip for an active-clamp forward converter (ACFC) Power Block for data center applications is developed. While the ACFC Power Block converts 12-48 V intermediate DC bus voltage to a digital PoL voltage, the gate timing control and driver chip can optimize PCE and reduce the system form factor.
| Identifer | oai:union.ndltd.org:columbia.edu/oai:academiccommons.columbia.edu:10.7916/j82x-az45 |
| Date | January 2022 |
| Creators | Kim, Dongkwun |
| Source Sets | Columbia University |
| Language | English |
| Detected Language | English |
| Type | Theses |
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