The stacking of silicon wafers and processing of through-silicon vias, which is often called 3DIC Technology, has opened up the possibility of improving the performance of circuits that are wire-delay limited. This project explores the design of Static Random Access Memories (SRAM), an important building block in 3DICs. Detailed transistor-level and layout design-data are presented for bit-cells and peripheral circuitry. Two different architectures are tested and their parameters are compared. The thesis concludes with the decision of which architecture proved to be the better one for 1Kb SRAM.
| Identifer | oai:union.ndltd.org:NCSU/oai:NCSU:etd-05192008-121657 |
| Date | 28 May 2008 |
| Creators | Modi, Kaushal Manesh |
| Contributors | Dr Paul Franzon, Dr William Rhett Davis, Dr Winser Alexander |
| Publisher | NCSU |
| Source Sets | North Carolina State University |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://www.lib.ncsu.edu/theses/available/etd-05192008-121657/ |
| Rights | unrestricted, I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dis sertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. |
Page generated in 0.0028 seconds