<p>The gap between processor speeds and memory speeds is increasing. The performance of supercomputers and the scalability of multiprocessor systems is very dependent on the memory system speed.</p> <p>A cache system helps to narrow the processor/memory speed gap, but cannot completely decouple the processor from slow memory.</p> <p>The optimization of main memory performance and the use of a deep multilevel cache hierarchy are proposed here to bridge the processor/memory latency gap.</p> <p>A novel design that combines optimized bank interleaving with several main memory (DRAM) timing modes to increase memory performance is presented. Four different protocols based on this design are proposed and investigated.</p> <p>Enforcing the inclusion property for multi-level caches is proposed. A new design that uses three level caches is preserved and three different models are given.</p> <p>A design flow graph that makes the design of a multi-level memory system simpler and more flexible is introduced. Selected traces that match real workloads running on a wide range of computers are used to calculate realistic overall system performance.</p> / Doctor of Philosophy (PhD)
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/6357 |
| Date | 09 1900 |
| Creators | Mekhiel, Nassief Nagi |
| Contributors | McCrackin, Daniel, Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Detected Language | English |
| Type | thesis |
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