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High-Speed Transceiver Design in CMOS using Multi-level (4-PAM) Signaling

The design of a 4 Gbps serial link transceiver in 0.35µm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming 879.4 mW of power from a 3.3 V supply.

Identiferoai:union.ndltd.org:NCSU/oai:NCSU:etd-01062003-204633
Date22 January 2003
CreatorsJoseph, Balu
ContributorsDr. Gianluca Lazzi, Dr. Wentai Liu, Dr. Rhett Davis
PublisherNCSU
Source SetsNorth Carolina State University
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://www.lib.ncsu.edu/theses/available/etd-01062003-204633/
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