A novel approach to high level synthesis of A sc SICs based on a data driven execution model is presented. The synthesis procedure is directed at producing highly parallel A sc SICs providing high throughput using pipelining. The major benefits of our approach are its potential for higher speed, ease of design, and ease of verification and testing. The application is specified in the functional language S sc ISAL, which is translated to a data flow graph (DFG). This DFG is then directly mapped onto silicon, resulting in a circuit which resembles the DFG itself. Next, area minimization and buffer allocation steps are carried out to meet specified area and performance requirements. The design for testability features based on functional description are used to enhance controllability and observability. A hierarchical test generation procedure based on functional fault model is developed. Synthesis tools incorporating all these features are implemented.
| Identifer | oai:union.ndltd.org:UMASS/oai:scholarworks.umass.edu:dissertations-8164 |
| Date | 01 January 1991 |
| Creators | Patel, Baiju V |
| Publisher | ScholarWorks@UMass Amherst |
| Source Sets | University of Massachusetts, Amherst |
| Language | English |
| Detected Language | English |
| Type | text |
| Source | Doctoral Dissertations Available from Proquest |
Page generated in 0.0024 seconds