Far ranging developments in VLSI and fiber optic technology have begun to form the basis for integrated networks that provide many new multimedia and real-time services. These services involve the combined use of different media such as voice, video, image and data. Supporting these applications requires the resolution of a number of issues within the network to provide the quality of service (QOS) guarantees. In this dissertation, we address four specific problems related to the design, and performance of high-speed packet switches and integrated services. At the heart of a high-speed network are the switching fabrics. The architecture and queueing strategy of the switch fabric contributes significantly to the QOS of applications. In the area of switch fabric design, we focus on a buffering strategy that is simple to implement, yet provides performance comparable to complex buffering mechanisms. We study the performance of different buffering strategies using analytical models and simulations. Turning our attention to the multimedia applications, specifically video traffic which is expected to contribute to a majority of the traffic on these integrated networks, we study quality of service issues. We examine the effects of packet loss on the quality of compressed video. We show that trade-offs are involved in total bit rate and susceptibility to packet loss. We propose different techniques to reduce packet loss and to mitigate the effect of packet loss on picture quality. In applications involving the use of video or other real-time applications there is a need to schedule different classes of traffic to provide priority to time-constrained applications. We propose four new scheduling policies that approximate the behavior of the optimal minimum laxity scheduling policy. The computational complexity of all four policies is independent of the number of packets in queue. Further, our results indicate that the performance of the best of the four policies is within 5% of the optimal scheduling policy. Simulation of high-speed packet switches is computationally intensive. We demonstrate that parallel time-driven simulations can be effectively used for high-speed packet switch simulations which are inherently discrete time based. We develop, new processor synchronization and processor assignment techniques that exploit the topology of packet switches and parallelize the time-driven simulations to achieve near linear speedups.
| Identifer | oai:union.ndltd.org:UMASS/oai:scholarworks.umass.edu:dissertations-9032 |
| Date | 01 January 1995 |
| Creators | Goli, Praveen Kumar |
| Publisher | ScholarWorks@UMass Amherst |
| Source Sets | University of Massachusetts, Amherst |
| Language | English |
| Detected Language | English |
| Type | text |
| Source | Doctoral Dissertations Available from Proquest |
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