In conventional pipelined circuits there is only one data wave active in any pipeline stage at any time; therefore, the clock speed of the circuit is limited by the maximum stage delay in the circuit. In wave pipelining, the clock speed depends mostly on the difference between the longest and shortest path delays. In some circuit designs there are redundant elements to make the circuit less sensitive to noise, to provide higher signal driving capability, or other purposes. Also, some circuit designs include logic to detect the early completion of a computation, or to guarantee that the worst physical path delay does not equate to the worst computational delay. Prior tools for wave-pipelined circuits do not account for such design features. This research develops a computer-aided design tool to determine the maximum clock speed for wave pipelined circuits with redundant logic or where otherwise the internal circuit timing depends on the input signal values. Moreover, alternative design techniques are proposed to improve the performance of wave pipelined circuits. / Includes bibliographic references (leaves 39-41) / Thesis (M.S.)--Wichita State University, Dept. of Electrical and Computer Engineering. / "May 2006." / Includes bibliographic references (leaves 39-41)
| Identifer | oai:union.ndltd.org:WICHITA/oai:soar.wichita.edu:10057/383 |
| Date | 05 1900 |
| Creators | Ozgun, Recep |
| Contributors | Meyer, Fred J. |
| Publisher | Wichita State University |
| Source Sets | Wichita State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Format | x, 54 leaves : ill., digital, PDF file., 4086102 bytes, application/pdf |
| Rights | Access restricted to WSU students, faculty and staff, Copyright Recep Ozgun, 2006. All rights reserved. |
Page generated in 0.0014 seconds