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Detection of Variable Retention Time in DRAM

This thesis investigates a test method to detect the presence of Variable Retention Time (VRT) bits in manufactured DRAM. The VRT bits retention time is modeled as a 2-state random telegraph process that includes miscorrelation between test and use. The VRT defect is particularly sensitive to test and use conditions. A new test method is proposed to screen the VRT bits by simulating the use conditions during manufacturing test. Evaluation of the proposed test method required a bit-level VRT model to be parameterized as a function of temperature and voltage conditions. The complete 2-state VRT bit model combines models for the time-in-state and for the retention-time including miscorrelation. A copula is used to model the eect of miscorrelation between test and use. The proposed VRT test algorithm runtime is estimated as a function of VRT test coverage, test temperature and test voltage.

Identiferoai:union.ndltd.org:pdx.edu/oai:pdxscholar.library.pdx.edu:open_access_etds-3103
Date19 November 2014
CreatorsKumar, Neraj
PublisherPDXScholar
Source SetsPortland State University
Detected LanguageEnglish
Typetext
Formatapplication/pdf
SourceDissertations and Theses

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